1. Field of the invention
The present invention relates to a semiconductor device in which a DRAM, a SRAM, and a logic circuit are mixedly mounted.
2. Description of Related Art
In a conventional function wiring of a SRAM, three wiring layers are used (see Japanese Unexamined Patent Application Publication No. 2005-56993 (Harada), for example). As shown in FIG. 7, a semiconductor device disclosed in Harada includes a product integrated circuit having a desired function, and a first SRAM circuit 112 and a second SRAM circuit 113 used for a process failure analysis. The first SRAM circuit 112 includes a SRAM cell of a C-MOS structure and realizes a SRAM function with a wiring formed of a first wiring layer M1 to a third wiring layer M3, vias (1 Via and 2 Via), and a contact CO, all of which are formed on the SRAM cell. Note that another wiring that has no direct relation with the SRAM function is arranged in a fourth wiring layer M4 to a sixth wiring layer M6 of the first SRAM circuit 112. A wiring connecting between transistors of the SRAM cell (cross couple connection) is formed in the first wiring layer M1. A wordline is formed in the second wiring layer M2. A digit (bit) line is formed in the third wiring layer M3.
The second SRAM circuit 113 also includes the SRAM cell of the C-MOS structure as the first SRAM circuit 112 does. And the second SRAM circuit 113 realizes the SRAM function with a wiring formed of the fourth wiring layer M4 to the sixth wiring layer M6, and vias (3 Via to 5 Via), all of which are formed above the SRAM cell. A vertical via and a dotted wiring are formed in the first wiring layer M1 to the third wiring layer M3, the vias (1 Via, 2 Via), and the contact CO of the second SRAM circuit 113. The vertical via and the dotted wiring causes the wiring having the SRAM function composed of the the first wiring layer M1 to the third wiring layer M3, the vias (1 Via, 2 Via), and the contact CO in the first SRAM circuit 112 to be arranged in the fourth wiring layer M4 to the sixth wiring layer M6 and the vias (3 Via to 5 Via). In the second SRAM circuit 113, a wiring connecting between the transistors of the SRAM cell (cross couple connection) is formed in the fourth wiring layer M4, the wordline is formed in the fifth wiring layer M5, and the digit line is formed in the sixth wiring layer M6, for example.
In the failure analysis of a semiconductor 110, a bitmap analysis that is applied to the failure analysis of memory products is applied to the first SRAM circuit 112 and the second SRAM circuit 113. In general, the SRAM circuit has three wiring layers. Therefore, it is possible to identify which wiring layer of the three wiring layers that forms the SRAM function has a failure by applying the bitmap analysis to the SRAM circuit.
As stated above, the SRAM circuit typically has three wiring layers. Therefore, in a logic process in which the DRAM is mixedly mounted, a process for forming a bitline and a capacity is added between a process for forming a contact of a general logic process and a process for forming the first wiring layer (M1) in the DRAM region. And in the region other than the DRAM region, a three-tiered structure in which a capacitive contact and a stack contact are mounted on the contact of a logic is built to connect to the first wiring layer M1 (see S. Arai et al., A0. 13 μm Full Metal Embedded DRAM Technology Targeting on 1.2 V, 450 MHz Operation, IEEE, 2001, for example). The DRAM is classified into two types, a stack type and a trench type, in terms of a structure of a capacitor (see H. Yoshimura et al., ACMOS Technology Platform for 0.13 μm Generation SOC (System on a Chip) IEEE, 2000 Symposium on VLSI Technology Digest Papers p. 144-145, for example). Note that the stack-type DRAM is explained here.
FIGS. 8 to 11 are diagrams showing a related semiconductor device in which the DRAM is mixedly mounted. FIG. 8 is a schematical cross sectional view and FIG. 9 is a plan view of the SRAM region. FIG. 10A is a cross sectional view showing X1 to X14 shown in FIG. 9, and FIG. 10B is a view of an equivalent circuit. FIG. 11A is a plan view of the first wiring layer and a layer below the first wiring layer, and FIG. 11B is a plan view of the layer above the first wiring layer.
A semiconductor substrate includes a DRAM region A11, a logic region A12, and a SRAM region A13. The logic region A12 is a region in which a sense amplifier other than a memory is formed, for example. In addition, a transistor and a capacitive element are formed using the substrate and the first to fourth interlayer insulating layers 210, 220, 230, 240 formed on the substrate, and the three wiring layers M1 to M3 are formed on the upper layer. A diffusion layer 214 that is a source and a drain and a isolation field oxide 213 are formed below the first interlayer insulating layer 210 as shown in FIG. 10A. A gate electrode 212 is formed above the diffusion layer 214 and the like. As shown in FIG. 8, contacts 211, 223, 235 (see contact C11 in FIG. 10A) connecting the diffusion layer 214 and the first wiring layer M1 are formed to penetrate through the first to fourth interlayer insulating layers, 210, 220, 230, and 240.
In the DRAM region All, the third interlayer insulating layer 230 and the fourth interlayer insulating layer 240 are provided to form a capacitive element 231 formed of a lower electrode 232, a dielectric film 233, and an upper electrode 234. On the other hand, in the SRAM region, a stack contact 235 is provided penetrating through the third interlayer insulating layer 230 and the fourth interlayer insulating layer 240. As will be clear, the contacts connected to each diffusion layer or to the gate have the three-tiered structure in the SRAM region A13.
As shown in FIGS. 10A and 10B, the first wiring layer M1 includes a wiring 251 (M1) and a connection wiring (relay pad) 252. The wiring 251 (M1) connects the transistors D1 and L1 and is formed in the first wiring layer M1. The connection wiring (relay pad) 252 connects the contact C11 and the via V1 and is formed in the first wiring layer M1. The second wiring layer M2 is formed on the first wiring layer M1 through the via V1. As shown in FIGS. 10A and 10B, the second wiring layer M2 has a wordline WL (M2) and a relay pad 261 (M2) connecting the vias V1 and V2. In addition, the third wiring layer M3 is formed on the second wiring layer M2 through the via V2. The third wiring layer M3 includes a bit line BL (M3) and a power supply line VDD (M3).
As shown in FIGS. 12 and 13, the wordline WL of the second wiring layer may be linearly formed depending on layouts of the wiring layers M1 to M3.
However, in the related SRAM, the cross couple connection is formed using the first wiring layer M1, and the diffusion layer and the first wiring layer M1 used to connect nodes are connected by the contacts built in the three-tiered structure (C11). Then the wiring layer such as the wordline is provided on the first wiring layer M1. Therefore, all the wiring layers from the first to third wiring layers, M1 to M3, are needed to form the SRAM cell. Moreover, the wiring M3 for inter-macro connection cannot be provided in the SRAM cell region because the third wiring layer M3 is needed to form the SRAM cell. Therefore, there are problems that a wiring delay can be occurred and a chip size can be increased because it is needed to perform wiring by bypassing the SPAM cell region when the inter-macro connection is performed in the third wiring layer M3.